STK1002/PLL filters
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The PLL filters are used by the two PLL's in AP7000 to generate the CPU frequency and generic clock signals.
The resistors and capacitors making up the two PLL filters are placed underneath AP7000 on the STK1002 PCB.
Schematics
Notes to designer
Default settings for the two PLL filters are tuned for the use listed in the table below. Please refer the ap7000 datasheet for a description of the PLL's in AP7000.
Filter | Fosc | DIV | MUL | Fn (PLL bandwidth) | Fout | R2/R3 | C8/C10 | C7/C9 |
---|---|---|---|---|---|---|---|---|
PLL0 | 20 MHz | 4 | 20 | 20 | 100 MHz | R2= 470 OHM | C8= 2.2nF | C7= 22nF |
PLL1 | 20 MHz | 1 | 7 | 20 | 140 MHz | R3= 150 OHM | C10= 8.2nF | C9= 68nF |
The output frequency is calculated as follows: Fout = (Fosc / DIV ) * MUL