STK1002/PLL filters

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The PLL filters are used by the two PLL's in AP7000 to generate the CPU frequency and generic clock signals.

The resistors and capacitors making up the two PLL filters are placed underneath AP7000 on the STK1002 PCB.

Image:STK1002PLLFilters.jpg

Schematics

Image:STK1002PLLFiltersSch.gif

Notes to designer

Default settings for the two PLL filters are tuned for the use listed in the table below. Please refer the ap7000 datasheet for a description of the PLL's in AP7000.

FilterFoscDIVMULFn (PLL bandwidth)FoutR2/R3C8/C10C7/C9
PLL020 MHz42020100 MHzR2= 470 OHMC8= 2.2nFC7= 22nF
PLL120 MHz1720140 MHzR3= 150 OHMC10= 8.2nFC9= 68nF

The output frequency is calculated as follows: Fout = (Fosc / DIV ) * MUL

Static version created: 2007-03-07
Copyright (c) 2007 Atmel Corporation