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The Peripheral DMA Controller (PDC)

The PDC is a simple DMA controller which is typically used with relatively low-speed peripherals such as the USART or SPI modules.

A PDC channel is controlled through a set of I/O registers mapped into the address space of the peripheral it is connected to. These registers are typically mapped from offset 0x100 and onwards.

Describing a block of memory takes two parameters: A base address (pointer) and a size (counter). This pair of parameters is typically replicated four times: TX/RX current pointer/counter and TX/RX next pointer/counter. The next pair is loaded into the current pair whenever the current block transfer is complete, i.e. the counter reaches zero. If the current block is empty when the next block is loaded, the parameters are loaded into the current block immediately.

There is also a register for individually enabling/disabling the TX and RX parts of the channel and a register showing whether or not TX and RX is enabled.

r1 - 2006-05-28 - 13:12:42 - HaavardSkinnemoen
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